1. Field of the Invention
The present invention relates to a level shifter circuit and an EEPROM (electrically erasable and programmable read only memory) using the same in a decorder section thereof.
2. Description of the Related Art
As well known in the art an EEPROM, one type of a nonvolatile semiconductor memory, is so configured that it constitutes a matrix array of cells and the cell of a given address is accessed by a row decoder (row selection) and column decoder (column selection).
FIG. 5 shows a circuit arrangement of a conventional EEPROM.
The erase, write and read operations of EEPROM will be explained below with reference to FIG. 5. An explanation given below is based on the description of Yasoji Suzuki "Semiconductor MOS Memory and How to Use It" published, by NIKKAN KOGYO Newspaper Publishing Company.
(1) Erase operation (electron injection)
First, the cell configuration of EEPROM per se will be explained below prior to the explanation of the erase operation.
Each of cells 00 to 30 in the cell matrix array CM is comprised of eight cells (8 bit segments) 000 to 007 as shown enlarged by a representing cell 00 in FIG. 5.
The control gates of memory transistors MT of the eight cells 000 to 007 in a lateral array are commonly connected and they are also connected to a select signal C.sub.0 line via a transistor G.sub.00.
It is to be noted that, though an output RA.sub.0 of a row decoder RD is commonly input to the gate electrodes of select transistors ST of all cells 00, 10, 20 and 30 in a lateral array, the signal C.sub.0 coming via the transistor G.sub.00 is supplied only to the control gate electrodes of the eight memory transistors in the lateral cell array.
Though the output RA.sub.0 of the row decoder RD is applied to the select gate electrode of the cell 10 as in the case of the cell 00, a C.sub.1 line signal is supplied via the transistor G.sub.10 to the control gate electrode of the memory transistor of the cell 10 unlike in the case of the cell 00.
This is because, except for a cell to be subjected to an erase operation, no high voltage is applied to the remaining cells at the erase operation.
The erase operation is performed as follows.
Let it be assumed that the cell 000 in the cell 00 is subjected to an erase operation. First, a signal "0" is applied to address input lines A.sub.0 and A.sub.1 of the row decoder RD and a high voltage 20 V is applied to an output line RA.sub.0. A voltage 0 V is applied to output lines RA.sub.1, RA.sub.2 and RA.sub.3. A signal "0" is applied to address input lines A.sub.2 and A.sub.3 of the column decoder CD and a voltage of 20 V is applied to an output line CA.sub.0 and a voltage 0 V is applied to output lines CA.sub.1, CA.sub.2 and CA.sub.3 of the column decoder CD.
Then a column select transistor Q.sub.0 and a transistor G.sub.00 of the cell 00 are turned ON, and an erase voltage signal .alpha. (=20 V) is applied to the control gate electrode of the cell 000 to that of the cell 007.
On the other hand, the bit line B.sub.00 takes a potential .beta. via a data column select transistor Tr.sub.0. Since here .beta.=0 V, each terminal of the cell 000 is placed in an erase (electron-injection) state. To be specific, a voltage "20 V" is applied to the select gate electrode and control gate electrode in the cell 000 and a voltage "0 V" is applied to the drain electrode of the select transistor ST.
At this time, the source electrode (shown by the mark of .quadrature. in FIG. 5) of the memory transistor MT is placed in a voltage level 0 V.
If any one of the bit lines B.sub.00 to B.sub.07 is given a level "0", an erase operation (electron injection) can be performed on the cells 000 to 007 in the cell 00 corresponding to that bit and a similar erase operation can also be performed on the other cells 01 to 33.
Since the control gate electrode of the cell 10 (actually 8 in number) adjacent the cell 00 is RA.sub.0 =20 V, the transistor G.sub.10 is turned ON but the control gate electrodes of the eight memory transistors in the cell 10 do not become a high voltage because a column select transistor Q.sub.1 is turned OFF. Therefore, it is possible to prevent the adjacent cell from being inadvertently erased (electron-injected) and hence to achieve high reliability at the erase operation.
(2) Write operation (electron release)
Performing a write operation on the cell 000 in the cell 00 will be explained below.
Let it be assumed that, as in the case of the erase operation, a signal "0" is applied to the address input lines A.sub.0 and A.sub.1 and a signal "0" is applied to the address input lines A.sub.2 and A.sub.3. In this state, .alpha.=0 V and .beta.=20 V.
Through a column select transistor Q.sub.0 and the transistor G.sub.00 in the cell 00 a voltage 0 V is applied to the control gate electrode of the cell 000 and a voltage 20 V is applied via a data column select transistor Tr.sub.0 to the bit line B.sub.00.
20 V=RA.sub.0 is applied to the select gate electrode of the cell 000 and a write mode is involved. Electrons are released from the floating gate electrode of the memory transistor MT.
At this time, it is assumed that the source electrode of the memory transistor MT is placed in a 5 V level. In this way, a write operation (electron release) is carried out.
A write operation (electron release) is performed on the cell 000 and the bit line B.sub.00 becomes a 20 V level. However, this effect, being exerted on the immediately overlying cell 01, will cause an operation error. To be specific, due to a high voltage (20 V) being applied to the bit line B.sub.00 the cell 01 produces an operation error upon releasing electrons.
To prevent this adverse effect, the select transistor ST is added to each cell and, when a voltage 0 V appears on the output line RA.sub.1 of the row decoder RD, the select transistor ST is turned OFF, thus eliminating such an effect resulting from high voltage involved.
Unlike an EPROM (erasable and programmable ROM), as set out above, EEPROM contains cells each comprised of two transistors so as to prevent any high voltage from being applied to those non-selected cells at a write operation and any data in those non-selected cells from being output to a bit line at a read operation.
(3) Read Operation
A high voltage (20 V) is not used in a read operation mode. A selected level shifter circuit LS of the decoder has its output set to be 5 V and a non-select shifter circuits LS of the decoder have their outputs to be set to be 0 V. Reading data out of the cell 000 in the cell 00 will be explained in more detail below.
When the cell 000 is to be selected, as in the case of the erase and write operations, a signal "0" is applied to the address input line A.sub.0 and A.sub.1 or to the address input lines A.sub.2 and A.sub.3. An output line RA.sub.0 of the row decoder RD is set to be 5 V and an output line CA.sub.0 of the column decoder CD is set to be 5 V.
In this mode, .alpha.=0 V.
In this state, the transistors Q.sub.0 and Tr.sub.0, as well as the transistors G.sub.00 and select transistor ST, are turned ON and, therefore, a voltage .alpha.=0 V is applied to the control gate electrode in the cell 000 via the transistors Q.sub.0 and G.sub.00.
If, in this state, the cell 000 have been served as an erase (electron injection) cell, the memory transistor MT, being an enhancement type, is turned OFF.
Therefore, the cell 000 delivers no signal to the bit line B.sub.00. The bit line B.sub.00 is held at an about 1 V potential level by a pull-up element PU located at an upper side. The potential level of 1 V is detected by a sense circuit S as being data "1".
If, on the other hand, the cell 000 have been served as a write cell (electron release), the memory transistor MT, being a depletion type, is turned ON even in the event of the gate being 0 V.
Thus the bit line B.sub.00 is pulled down toward a GND side via the select transistor ST. Since the pull-up element PU is connected to the tip of the bit line B.sub.00, a DC path is created between the pull-up element PU and the cell 000 and a potential on the bit line B.sub.00 drops down to about 0.2 V.
The potential level of 0.2 V is detected, by the sense circuit S, as being data "0".
In this way, the data "1" and "0" are read out of the cell 000 and a similar read operation can also be performed on the other cells.
Next, the level shifter circuit LS in the EEPROM circuit arrangement of FIG. 5 will be explained below in more detail and in relation with the present invention. FIG. 6 shows a symbol form of the level shifter circuit LS and FIG. 7 shows its circuit arrangement.
As shown in FIG. 7, the level shifter circuit LS comprises an N-channel D type transistor TN1 having a source electrode and a drain electrode connected to an input terminal IN and an output terminal OUT, respectively, and a gate electrode supplied with an inverted replica (Erase+Write) of a signal Erase+Write, that is, a signal 0 V at a time of erasing or writing operation and 5 V at the other operation, and a charge pump circuit CP connected to the output terminal OUT.
FIG. 8 shows one form of the charge pump circuit CP comprising an N-channel I type transistor TN2 and N-channel E type transistors TN3 and TN4.
FIGS. 9A and 9B and 10A and 10B are explanative views for explaining the operation of the level shifter circuit shown in FIGS. 7 and 8. The operation of the level shifter circuit incorporated into EEPROM (FIG. 5) will be explained below with reference to FIGS. 9A, 9B and 10A, 10B.
(1) Read Operation
As shown in FIG. 9A, an inverted replica (Erase+Write) of a signal Erase+Write is set to be 5 V and, therefore, an input signal 5 V is delivered to an output (5 V) via an N-channel D type transistor TN1 in a selected level shifter mode.
As shown in FIG. 10A, an input 0 V is delivered, via an N-channel D type transistor TN1, to an output (0 V) in a non-selected level shifter mode.
In the read operation, a charge pump circuit CP is set in a non-active state.
Here, the D type transistor TN1 is used as a means for preventing a voltage which is dropped by a portion V.sub.TH from an input voltage from appearing on the output side and for positively sending the input voltage to an output side. This is achieved since a threshold voltage (V.sub.TH) of the D type transistor is a negative threshold voltage -V.sub.TH.
(2) Erase/Write Operation
As shown in FIG. 9B, an inverted replica (Erase+Write) of a signal Erase+Write is set to a 0 V and an input 5 V is delivered via an N-channel D type transistor TN1 and appears as an output 2 V (V.sub.TH of a D type transistor TN1) in a selected level shifter mode. Only at the time of an erasing write operation, the voltage 2 V is boosted up by a charge pump circuit CP to 20 V (=Vpp).
As shown in FIG. 10B, an input signal 0 V is delivered via an N-channel D type transistor TN1 to an output (=0 V) in a non-selected level shifter mode.
Even in this case the charge pump circuit CP is in an active state and the input signal 0 V is not boosted up and appears as an output 0 V.
The above is an explanation concerning the operation of the level shifter circuit LS in EEPROM.
Here three types of N-channel transistors are required for the level shifter circuit LS:
a D type transistor having a negative threshold voltage (-V.sub.TH), an I type transistor having a neutral threshold voltage (V.sub.TH .perspectiveto.0 V) and an E type transistor having a positive threshold voltage (+V.sub.TH)
In the form of the EEPROM circuit shown in FIG. 5 the N-channel D type transistor is employed for the level shifter circuit LS only. In order to fabricate the N-channel D type transistor it is necessary, from the manufacturing process of an LSI (large scale integrated circuit), that an additional 1PEP (Photoengraving process) be imparted to the D type V.sub.TH alignment ion implantation process.
Put it in another way, since the conventional EEPROM circuit uses an N-channel D type transistor for the level shifter circuit, one more 1PEP process is required in the LSI fabrication process, thus resulting in an increase in chip cost, an increase in the manufacturing time period and a drop in yield.